general description the max3205e/max3207e/max3208e low-capaci-tance, ?5kv esd-protection diode arrays with an inte- grated transient voltage suppressor (tvs) clamp are suitable for high-speed and general-signal esd protec- tion. low input capacitance makes these devices ideal for esd protection of signals in hdtv, pc monitors (dvi , hdmi ), pc peripherals (firewire , usb 2.0), server interconnect (pci express , infiniband ), datacom, and interchassis interconnect. each channelconsists of a pair of diodes that steer esd current puls- es to v cc or gnd. the max3205e/max3207e/max3208e protect against esd pulses up to 15kv human body model, ?kv contact discharge, and 15kv air-gap discharge, as specified in iec 61000-4-2. an integrated tvs ensures that the voltage rise seen on v cc during an esd event is clamped to a known voltage. these devices have a2pf input capacitance per channel, and a channel-to- channel capacitance variation of only 0.05pf, making them ideal for use on high-speed, single-ended, or dif- ferential signals. the max3207e is a two-channel device suitable for usb 1.1, usb 2.0 (480mbps), and usb otg applica- tions. the max3208e is a four-channel device for ethernet and firewire applications. the max3205e is a six-channel device for cell phone connectors and svga video connections. the max3205e is available in 9-bump, tiny wafer-level package (wlp) and 16-pin, 3mm x 3mm, thin qfn packages. the max3207e is available in a small 6-pin sot23 package. the max3208e is available in 10-pin ?ax and 16-pin, 3mm x 3mm tqfn packages. all devices are specified for the -40? to +125? automo-tive operating temperature range. applications dvi input/output protectionset-top boxes pdas/cell phones graphics controller cards displays/projectors high-speed, full-speed and low-speed usb port protection firewire ieee 1394 ports consumer equipment high-speed differential signal protection features ? low input capacitance of 2pf typical ? low channel-to-channel variation of 0.05pf from i/o to i/o ? high-speed differential or single-ended esd protection 15kvChuman body model 8kvCiec 61000-4-2, contact discharge 15kvCiec 61000-4-2, air-gap discharge ? integrated transient voltage suppressor (tvs) ? optimized pinout for minimized stub inductance on controlled-impedance differential- transmission line routing ? -40c to +125c automotive operating temperature range ? wlp packaging available max3205e/max3207e/max3208e dual, quad, and hex high-speed differential esd-protection ics ___________________________________________________ _____________ maxim integrated products 1 ordering information 19-3361; rev 3; 7/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. firewire is a registered trademark of apple inc. pci express is a registered service mark of pci-sig corporation. dvi is a trademark of digital display working group. hdmi is a registered trademark and registered service mark of hdmi licensing, lcc. infiniband is a trademark and service mark of infiniband trade association. ?ax is a registered trademark of maxim integrated products, inc. typical operating circuit and pin configurations appear at end of data sheet. part temp range pin-package max3205e awl+t -40c to +125c 9 wlp max3205eate+ -40c to +125c 16 tqfn-ep* max3207e aut+t -40c to +125c 6 sot23 max3208e aub+ -40c to +125c 10 max max3208eate+ -40c to +125c 16 tqfn-ep* selector guide part esd-protected i/o ports top mark max3205eawl+t 6 ain max3205eate+ 6 aco max3207eaut+t 2 abvg max3208eaub+ 4 max3208eate+ 4 acn + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. * ep = exposed pad. downloaded from: http:///
max3205e/max3207e/max3208e dual, quad, and hex high-speed differential esd-protection ics 2 __________________________________________________ _____________________________________ absolute maximum ratings electrical characteristics (v cc = +5v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +5v and t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: parameters are 100% production tested at +25?. limits over temperature are guaranteed by design only. note 2: idealized clamp voltages. see the applications information section for more information. note 3: guaranteed by design, not production tested. v cc to gnd ...........................................................-0.3v to +6.0v i/o_ to gnd ................................................-0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70?) 6-pin sot23 (derate 8.7mw/? above +70?)............696mw 9-bump wlp (derate 14.1mw/? above +70?).............0mw 10-pin ?ax (derate 5.6mw/? above +70?) ...........444mw 16-pin tqfn (derate 20.8mw/? above +70?) .......1667mw operating temperature range .........................-40? to +125? storage temperature range .............................-65? to +150? junction temperature .....................................................+150? lead temperature (excluding wlp; soldering, 10s) .......+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units supply voltage v cc 0.9 5.5 v supply current i cc 1 100 na diode forward voltage v f i f = 10ma 0.65 0.95 v positive transients v cc + 25 t a = +25c, 15kv human body model, i f = 10a negative transients -25 positive transients v cc + 60 t a = +25c, 8kv contact discharge (iec 61000-4-2), i f = 24a negative transients -60 positive transients v cc + 100 channel clamp voltage (note 2) v c t a = +25c, 15kv air-gap discharge (iec 61000-4-2), i f = 45a negative transients -100 v channel leakage current -0.1 +0.1 a max3205eawl+t max3207eaut+t 2.5 3 max3205eate+ max3208eate+ 2.7 3.2 channel i/o capacitance v cc = +3.3v, bias of v cc / 2 max3208eaub+ 2.6 3.1 pf channel i/o to i/o variation in capacitance c in v cc = +3.3v, bias of v cc / 2, c i/o_ to gnd 0.05 pf transient suppressor v cc capacitance to gnd 10 pf esd trigger voltage dv/dt 1v/ns (note 3) 9 v downloaded from: http:///
max3205e/max3207e/max3208e dual, quad, and hex high-speed differential esd-protection ics _______________________________________________________________________________________ 3 clamp voltage vs. dc current max3205e toc01 dc current (ma) clamp voltage (v) 130 110 90 70 50 30 0.5 0.7 0.9 1.1 1.3 1.50.3 10 150 i/o_ to v cc gnd to i/o_ leakage current vs. temperature max3205e toc02 temperature ( c) leakage current (pa) 80 40 0 10 100 1000 10,000 1 -40 120 input capacitance vs. input voltage max3205e toc03 input voltage (v) input capacitance (pf) 4 3 2 1 1 2 3 40 05 typical operating characteristics (v cc = +5v, t a = +25?, unless otherwise noted.) pin description pin max3205e max3207e max3208e tqfn-ep wl p sot23 max tqfn-ep name function 4, 5, 7, 12, 13, 15 a2, a3, b1, b3, c1, c2 1, 4 1, 4, 6, 9 4, 7, 12, 15 i/o_ esd-protected channel 1, 3, 6, 8, 9, 11, 14, 16 3, 6 2, 5, 7, 10 1, 3, 5, 6, 8, 9, 11, 13, 14, 16 n.c. no connection. not internally connected. b2 n.c. no connection. the solder sphere is omitted from this location (see the package information section). 2 a1 2 3 2 gnd ground. connect gnd with a low-impedance connection to the ground plane. 10 c3 5 8 10 v cc power-supply input. bypass v cc to gnd with a 0.1f ceramic capacitor as close to the device as possible. ep exposed pad (tqfn only). connect ep to gnd. downloaded from: http:///
max3205e/max3207e/max3208e detailed description the max3205e/max3207e/max3208e low-capacitance,?5kv esd-protection diode arrays with an integrated transient voltage suppressor (tvs) clamp are suitable for high-speed and general-signal esd protection. low input capacitance makes these devices ideal for esd protection of signals in hdtv, pc monitors (dvi, hdmi), pc peripherals (firewire, usb 2.0), server interconnect (pci express, infiniband), datacom, and interchassis interconnect. each channel consists of a pair of diodes that steer esd current pulses to v cc or gnd. the max3207e, max3208e, and max3205e are two, four,and six channels (see the functional diagram ). the max3205e/max3207e/max3208e are designed towork in conjunction with a device? intrinsic esd pro- tection. the max3205e/max3207e/max3208e limit the excursion of the esd event to below 25v peak voltage when subjected to the human body model waveform. when subjected to the iec 61000-4-2 waveform and contact discharge, the peak voltage is limited to ?0v. the peak voltage is limited to 100v when subjected to air-gap discharge. the device protected by the max3205e/max3207e/max3208e must be able to withstand these peak voltages, plus any additional volt- age generated by the parasitic of the board. a tvs is integrated into the max3205e/max3207e/ max3208e to help clamp esd to a known voltage. this helps reduce the effects of parasitic inductance on the v cc rail by clamping v cc to a known voltage during an esd event. for the lowest possible clamp voltage dur-ing an esd event, placing a 0.1? capacitor as close to v cc as possible is recommended. dual, quad, and hex high-speed differential esd-protection ics 4 __________________________________________________ _____________________________________ max3207e v cc gnd i/o1 i/o2 max3208e v cc gnd i/o1 i/o2 i/o3 i/o4 max3205e v cc gnd i/o1 i/o2 i/o5 i/o6 i/o3 i/o4 functional diagram downloaded from: http:///
applications information design considerations maximum protection against esd damage results fromproper board layout (see the layout recommendations section). a good layout reduces the parasitic seriesinductance on the ground line, supply line, and protect- ed signal lines. the max3205e/max3207e/max3208e esd diodes clamp the voltage on the protected lines during an esd event and shunt the current to gnd or v cc . in an ideal circuit, the clamping voltage (v c ) is defined as the forward voltage drop (v f ) of the protec- tion diode, plus any supply voltage present on the cath-ode. for positive esd pulses: v c = v cc + v f for negative esd pulses: v c =-v f the effect of the parasitic series inductance on thelines must also be considered (figure 1). for positive esd pulses: for negative esd pulses: where i esd is the esd current pulse. during an esd event, the current pulse rises from zeroto peak value in nanoseconds (figure 2). for example, in a 15kv iec 61000 air-gap discharge esd event, the pulse current rises to approximately 45a in 1ns (di/dt = 45 x 10 9 ). an inductance of only 10nh adds an addi- tional 450v to the clamp voltage and representsapproximately 0.5in of board trace. regardless of the device? specified diode clamp voltage, a poor layout with parasitic inductance significantly increases the effective clamp voltage at the protected signal line. minimize the effects of parasitic inductance by placing the max3205e/max3207e/max3208e as close to the connector (or esd contact point) as possible. a low-esr 0.1? capacitor is recommended between v cc and gnd in order to get the maximum esd protec- tion possible. this bypass capacitor absorbs thecharge transferred by a positive esd event. ideally, the supply rail (v cc ) would absorb the charge caused by a positive esd strike without changing its regulatedvalue. all power supplies have an effective output impedance on their positive rails. if a power supply? effective output impedance is 1 , then by using v = i x r, the clamping voltage of v c increases by the equa- tion v c = i esd x r out . a +8kv iec 61000-4-2 esd event generates a current spike of 24a. the clampingvoltage increases by v c = 24a x 1 , or v c = 24v. again, a poor layout without proper bypassing increas-es the clamping voltage. a ceramic chip capacitor mounted as close as possible to the max3205e/ max3207e/max3208e v cc pin is the best choice for this application. a bypass capacitor should also beplaced as close to the protected device as possible. vv l x di dt lx di dt cf d esd esd () () = + ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? () 2 13 vv v lx di dt lx di dt cc cf d esd esd () () =+ + ? ? ? ? ? ? + ? ? ? ? ? ? () 1 12 max3205e/max3207e/max3208e dual, quad, and hex high-speed differential esd-protection ics ___________________________________________________ ____________________________________ 5 l1 protectedline l3 d2 ground rail positive supply rail i/o_ d1 l2 figure 1. parasitic series inductance t r = 0.7ns to 1ns 30ns 60ns t 100% 90%10% i peak i figure 2. iec 61000-4-2 esd generator current waveform downloaded from: http:///
max3205e/max3207e/max3208e 15kv esd protection esd protection can be tested in various ways. themax3205e/max3207e/max3208e are characterized for protection to the following limits: ?5kv using the human body model ?kv using the contact discharge method specified in iec 61000-4-2 ?5kv using the iec 61000-4-2 air-gap discharge method esd test conditions esd performance depends on a number of conditions.contact maxim for a reliability report that documents test setup, methodology, and results. human body model figure 3 shows the human body model, and figure 4shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of inter- est, which is then discharged into the device through a 1.5k resistor. iec 61000-4-2 the iec 61000-4-2 standard covers esd testing andperformance of finished equipment. the max3205e/ max3207e/max3208e help users design equipment that meets level 4 of iec 61000-4-2. the main differ- ence between tests done using the human body model and iec 61000-4-2 is higher peak current in iec 61000-4-2. because series resistance is lower in the iec 61000-4-2 esd test model (figure 5), the esd- withstand voltage measured to this standard is general- ly lower than that measured using the human body model. figure 2 shows the current waveform for the ?kv, iec 61000-4-2 level 4, esd contact discharge test. the air-gap discharge test involves approaching the device with a charged probe. the contact discharge method connects the probe to the device before the probe is energized. dual, quad, and hex high-speed differential esd-protection ics 6 __________________________________________________ _____________________________________ charge-current- limit resistor discharge resistance storagecapacitor c s 100pf r c 1m r d 1.5k high- voltage dc source device under test figure 3. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing(not drawn to scale) i r 10% 0 0 amperes figure 4. human body model current waveform charge-current- limit resistor discharge resistance storagecapacitor c s 150pf r c 50m to 100m r d 330 high- voltage dc source device under test figure 5. iec 61000-4-2 esd test model downloaded from: http:///
layout recommendations proper circuit-board layout is critical to suppress esd-induced line transients (see figure 6). the max3205e/ max3207e/max3208e clamp to 100v; however, with improper layout, the voltage spike at the device can be much higher. a lead inductance of 10nh with a 45a current spike results in an additional 450v spike on the protected line. it is essential that the layout of the pc board follows these guidelines: 1) minimize trace length between the connector or input terminal, i/o_, and the protected signal line. 2) use separate planes for power and ground to reduce parasitic inductance and to reduce the impedance tothe power rails for shunted esd current. 3) ensure short low-inductance esd transient return paths to gnd and v cc . 4) minimize conductive power and ground loops. 5) do not place critical signals near the edge of the pc board. 6) bypass v cc to gnd with a low-esr ceramic capaci- tor as close to v cc as possible. 7) bypass the supply of the protected device to gnd with a low-esr ceramic capacitor as close to thesupply pin as possible. wlp applications information for the latest application details on wlp construction,dimensions, tape carrier information, printed circuit board techniques, bump-pad layout, and recommend- ed reflow temperature profile, as well as the latest infor- mation on reliability testing results, refer to application note 1891: wafer-level packaging (wlp) and its applications . chip information process: bicmos max3205e/max3207e/max3208e dual, quad, and hex high-speed differential esd-protection ics ___________________________________________________ ____________________________________ 7 v cc protected line negative esd-current pulse path to ground protected circuit gnd d1 i/o_ v c d2 l1 l3 l2 figure 6. layout considerations max3205e max3207e max3208e 0.1 f 0.1 f i/0_ i/0 i/0 line v cc v cc protected circuit typical operating circuit downloaded from: http:///
max3205e/max3207e/max3208e dual, quad, and hex high-speed differential esd-protection ics 8 __________________________________________________ _____________________________________ top view 16 15 14 13 9 10 11 12 n.c. v cc n.c. i/o2 4 3 2 1 i/o4 n.c. gnd n.c. 5678 n.c.n.c. i/o3 n.c. n.c.i/o1 n.c. n.c. max3208e tqfn 16 15 14 13 9 10 11 12 n.c. v cc n.c. i/o3 4 3 2 1 i/o6 n.c. gnd n.c. 5678 i/o5 n.c. i/o4 n.c. n.c.i/o1 n.c. i/o2 max3205e tqfn gnd i/o2 n.c. 1 6 n.c. 5v cc i/o1 max3207e sot23 234 1 23 4 5 10 98 7 6 n.c.i/o4 v cc n.c. i/o2 gnd n.c. i/o1 max3208e max i/o3 n.c. max3205e wlp (bumps on bottom) a2 a3 i/o5 a1 gnd i/o1 i/o2 i/o6 *ep*ep *connect ep to gnd. ++ + + b1 b3 i/o4 c1 c2 c3 v cc i/o3 pin configurations package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 9 wlp w91b1+5 21-0067 16 tqfn-ep t1633+4 21-0136 90-0031 6 sot23 u6+1 21-0058 90-0175 10 ?ax u10+2 21-0061 90-0330 downloaded from: http:///
max3205e/max3207e/max3208e dual, quad, and hex high-speed differential esd-protection ics maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 9 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 3 7/10 changed the 9 ucsp package to a 9 wlp package in the ordering information table, absolute maimum ratings , pin description table, and the pin configurations ; changed leaded packages to lead-free packages in the ordering information table; changed the max3205eawl+t part number and its top mark in the selector guide ; deleted all information in the chip information section except process: bicmos 1, 2, 3, 7, 8 downloaded from: http:///
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